`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/07/05 22:56:57
// Design Name: 
// Module Name: tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb(

    );

    reg clk;
    reg reset_n;
    wire [31:0] data;
    wire [31:0] addr_ir;
    
    top top(clk,reset_n,data,addr_ir);
    
    initial begin
        $readmemb("D:/vivado/riscv_cpu/riscv_cpu.srcs/sim_1/new/inst.txt",top.mem_inst.mem_inst);
    end

    initial begin
        clk = 0;
        forever begin
            #5 clk = ~clk;
        end
    end

    initial begin
        reset_n = 1;
        #15 reset_n = 0;
        #10 reset_n = 1;
    end

endmodule
